Conventionally, in a self-contained system, requested functions are more complicated while a processor is implemented for general purpose use, and a method for realizing the functions by software processing is proposed.
However, the requested functions are complicated in recent years, the computational complexity of software by a processor increases, and the power consumption of the processor also increases. On the other hand, it is important to reduce power consumption with smaller self-contained equipment, and solve a problem of a heat caused thereby.
Thus, methods for performing parallel processing have been proposed using a plurality of processors and a multicore processor chip. For example, a portion for dividing a program into function blocks for executing distributed functions, and parallel processing for expanding a loop process of a program in parallel and distributing loads are well known.
Assume that a processor of a system configured by a plurality of processors is referred to as a processor core, and each processor of a multicore processor chip is also referred to as a processor core.
Generally, when implementation is realized on a processor core, the number of parallel expansions of loop execution is statically divided by using all processor cores for the given number of processor cores.
In addition, it is known that the entire power consumption of a system implemented with a program having loop parallelism or a multicore processor chip can be reduced more effectively by performing loop division on the program having the loop parallelism and operating each processor core at a low frequency than by performing the operation at a high frequency using a single processor.
The phenomenon arises by the physical and electric characteristics of a processor core, and when the frequency is raised, the power consumption rises acceleratingly, but not proportionally.
However, the above-mentioned tendency refers to the characteristics of hardware, but does not refer to the optimum tendency when an application is performed by actual consumer products.
In the conventional compiler technology, the number of processor cores in the target execution environment is statically provided during compilation, and the code of each processor core generated by a compiler is fixedly allocated to an executing processor core.
In addition, a method for reducing power consumption can be a technique of dividing a power supply to each domain, locally stopping power supply, and changing a clock setting to each processor core.
However, the conventional technology is a result of implementing the electric superiority with a plurality of processors relative to a single processor and the efficiency of distributed load by expanding loop parallelism for a plurality of processor cores as separate events. It is not to obtain the optimum solution by totally considering the actual physical characteristic and the efficiency of the parallel execution, or to optically reduce the power consumption.